---------------------------------------------------------------------------------
  -- Design Name : Splits instrucion in opcode and addressing
  -- File Name   : IdInstrSplit.vhd
  -- Function    : Defines constants and components often used
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity IdInstrSplit is
    port (
      data:     in  word32;
      op:       out opCode;
      rd:       out regAddr;
      rs1:      out regAddr;
      rs2:      out regAddr;
      imm11:    out std_logic_vector(10 downto 0)
    );
end entity;

architecture behavioral of IdInstrSplit is
begin

  op(0) <= data(0);
  op(1) <= data(1);
  op(2) <= data(2);
  op(3) <= data(3);
  op(4) <= data(4);
  op(5) <= data(5);
  
  rd(4) <= data(6);
  rd(3) <= data(7);
  rd(2) <= data(8);
  rd(1) <= data(9);
  rd(0) <= data(10);
  
  rs1(4) <= data(11);
  rs1(3) <= data(12);
  rs1(2) <= data(13);
  rs1(1) <= data(14);
  rs1(0) <= data(15);
  
  rs2(4) <= data(16);
  rs2(3) <= data(17);
  rs2(2) <= data(18);
  rs2(1) <= data(19);
  rs2(0) <= data(20);
  
  imm11(10) <= data(21);
  imm11(9)  <= data(22);
  imm11(8)  <= data(23);
  imm11(7)  <= data(24);
  imm11(6)  <= data(25);
  imm11(5)  <= data(26);
  imm11(4)  <= data(27);
  imm11(3)  <= data(28);
  imm11(2)  <= data(29);
  imm11(1)  <= data(30);
  imm11(0)  <= data(31);
  

/* ovo ne radi :(
  op    <= data(0 to 5);
  rd    <= data(6 to 10);
  rs1   <= data(11 to 15);
  rs2   <= data(15 to 20);
  imm11 <= data(21 to 31);
*/
end architecture behavioral;
